Special Issue
Nano MVL Structures
p. 217-234
Guest Editorial:
Introduction to the Special Issue: Nano MVL Structures
Svetlana N. Yanushkevich and Vlad P. Shmerko
Abstract
Full Text (IP)
p. 235-248
Minimization of Ternary Reversible Logic Cascades Using a Universal Subset of Generalized Ternary Gates
Erik Curtis and Marek Perkowski
Abstract
Full Text (IP)
p. 249-266
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa and Yasuo Takahashi
Abstract
Full Text (IP)
p. 267-277
Multiple Path Switching Device Utilizing Size-Controlled Nano-Schottky Wrap Gates for MDD-Based Logic Circuits
Seiya Kasai, Tatsuya Nakamura and Yuta Shiratori
Abstract
Full Text (IP)