Body Biasing-A Circuit Level Approach to Reduce Leakage in Low Power 89 CMOS Circuits
Vandana Niranjan and Maneesha Gupta
CMOS circuits have scaled downward aggressively in each technology generation to achieve higher integration density and performance. With the current nanoscale technology trends in CMOS circuits, effective solutions have to be sought to reduce leakage power which is expected to dominate the chip’s total power consumption in the near future. These solutions must be sought in all design abstraction levels: system and architectural level, circuit level, and process/device level. This paper is a survey of various body biasing techniques which is a circuit level approach to reduce leakage in scaled CMOS circuits. This paper is first of its type where various body biasing techniques are covered together and will be useful for new researchers in this field.
Keywords: Low power CMOS, leakage power, Body biasing.