Significance of Nano Grain Sized Pt (100 Å) Along with Ti-W/Al-Cu Multi Level Metallisation to VLSI Substrate
V. Uma and R. Chandramani
In VLSI, metallization plays an important role to control the speed of the circuit, by virtue of resistance of the interconnection runners and also it controls flat band voltage between the substrate and multi metal layers. To minimize interconnection resistance and to save valuable chip area, multilevel metallization schemes have been proposed.
The monolayer Al-Cu, barrier layer Al-Cu/Ti-W and multilevel layers Al-Cu/Ti-W/Pt were deposited on Si using High Rate Magnetron Sputtering. In order to find the significance of the thin Pt layer, complete electrical, mechanical and micro structural analysis have been carried out for all the three samples.
From XRD, the phase of the samples remains the same as orthorhombic, but the grain size has drastically reduced from 80 nm (Al-Cu /Ti-W) to 26.76 nm in Al-Cu/Ti-W/Pt. Reduction in grain size due to the Pt layer enhances the mechanical stability in the substrate. For a given load, the Hardness value has increased and material has become tough. Constant resistivity value over a temperature range (room temperature to 200ºC) reveals the reduction of scattering center, voids and dislocation. This Pt/PtSi multi level matellization, which enhances the stability with low resistivity value is more appropriate for VLSI to reduce chip area significantly.