A New High-Performance Hybrid Full-Adder Design for VLSI Applications
Himanshu Chaurasia and Rajeevan Chandel
In the present paper, a new 1-bit hybrid full adder has been designed and proposed. The adder essentially consists of two modules, a 2-input exclusive-OR/exclusive-NOR gate, and a 2:1 multiplexer. The circuit performance is analysed in terms of metrics namely, power usage, transistor count, power-delay product (PDP), driving capability, and power-delay-number of transistors product (PDNP). Simulative analysis using Tanner EDA tools for CMOS 45 nm technology node shows that in comparison to prior hybrid full adder (HFA) designs, the suggested design offers superior space demand and power. The proposed circuit is also analysed with temperature variation and voltage scaling, to study its performance under varying conditions. In comparison to the existing one-bit hybrid full adder circuits, simulative analysis demonstrates that the proposed design displays lower power consumption, and lower PDNP value, thus is both energy and area efficient.
Keywords: Average power consumption, hybrid full adder, number of transistors, power-delay product, power-delay-number of transistor product, propagation delay