Design and Performance Analysis of Low-Power Arithmetic Circuits
Ritika Pandey and Pushpendra Sharma
The Low-Power Arithmetic Circuits is a research area that focuses on designing digital circuits that perform arithmetic operations while minimizing power consumption. This paper presents the design and performance analysis of low-power arithmetic circuits. The proposed circuits use low-power design techniques such as voltage scaling and clock gating to reduce power dissipation while maintaining acceptable performance. The circuits are implemented using CMOS technology and their performance is evaluated using Cadence software. Simulation results show that the proposed circuits have significantly lower power dissipation compared to conventional circuits, with a minimal impact on performance. The proposed circuits demonstrate the potential for reducing power consumption in arithmetic circuits, which can be beneficial for a range of applications including portable devices and embedded systems.
Keywords: XOR-XNOR gates, mMultiplexer, power dissipation, delay, powerdelay product