Performance Investigations of Novel Hybrid Junctionless Double Gate Transistor with Gate Engineering
Sachindra Bharti, Rohit Dhiman and Gargi Khanna
A novel hybrid double gate junctionless transistor with gate engineering using a dual gate oxide stack has been proposed to improve short-channel effects and gate controllability for digital applications. The performance analysis and comparison of the proposed device with a DGLK junctionless transistor has been reported, hybrid Junctionless double gate transistor device has provided SS 61.4 mV/decade which is close to the ideal value of 60 mV/decade and 27.91% improvement, DIBL of 7.368 mV/V with 88.487% improvement, off current is 35.6 fA/μm, which is nearly 1.6 ×10-6 times less and very high switching ratio of 1.648× 1010 which is 5.455 ×106 times higher than junctionless double gate transistor. Also, the effect of variations in gate dielectric, spacer length has been studied.
Keywords: Junctionless transistor, JnLT, Double gate junctionless transistor, DG-JnLT, Hybrid double gate junctionless transistor, HDG-JnLT, subthreshold swing, SS and drain induced barrier lowering -DIBL