Fast Locking and Area Efficient Differential Input Charge Pump Design for PLL Application
Nashra Khalid and Ram Chandra Singh Chauhan
Since Phase Locked Loops are widely used in wired and wireless communication systems. Performance of PLL largely depends on its charge pump block. Thus, to enhance PLL’s performance advancements in the charge-pump design must be done. In this paper a novel differential input based charge-pump circuit is introduced. . The central idea of the proposed design is to increase the overall output resistance which can keep the current mismatch as minimal as possible . With the use of differential input symmetric load of the charge-pump is achieved which reduces switching mismatch issues as the delay between turning on of PMOS and NMOS is eliminated. The current mismatch of this design is reported to be 0.78% over an output voltage range of 0 to 0.9V. The lock-in time is merely 16.61 ns with power dissipation of 278 μW. The noise response of the circuit is also good with phase noise of -111.07 dBc/Hz at an offset frequency of 10MHz. The circuit is designed in CADENCE VIRTUOSO platform for 90nm technology at a supply voltage of 1.2V.
Keywords: Phase locked loop, charge pump, phase noise, current mismatch, high-speed