Reduction of Leakage Parameters in 14T Full Subtractor Using GDI Technique
Vishwas Mishra and Shyam Akashe
With the advancement of technology in VLSI, various significant design methods of structuring VLSI circuits have been implemented. Different design styles follow CMOS, CPL, TG etc. GDI technique is also one them; that is more efficient consumes less power and area. This paper focuses on designing full subtractor using GDI technique as it overcomes the drawbacks of CMOS and other mentioned techniques and helped in designing low power combinational circuits. Along with low power consuming circuits, another factor that draws major attention is the area. The designers are continuously trying to place more and more components on single chip to form compact and portable devices. The proposed full subtractor consumes less area because with GDI technique in use, number of transistor employed is less as compared to conventional subtractor. The reason for this is that the components or gates used in implementing subtractor like XOR/XNOR/MUX are implemented with GDI technique.
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