JAPED 11.2-3, p. 263-269

Delay and Energy Efficiency Analysis of a 1-bit CMOS Full Adder
Manish Kumar

Delay and energy efficiency of a 1-bit CMOS full adder circuit is analyzed in this paper. Delay and energy efficiency analysis of the CMOS full adder circuit are carried out by varying various parameters such as temperature (T), supply voltage (V_DD), and oxide thickness (t_ox). Layout design and simulation of the full adder circuit are performed by using Microwind ver. 3.1 EDA tool and using BSIM4 MOS parameter model.

Keywords: Delay, power dissipation, oxide thickness, supply voltage, temperature.

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JAPED 11.2-3, p. 263-269

Call for Papers for JAPED Special Issue