Ultra Low Power Approximate Adder for Deep Learning Accelerator
G. R. Mahendra Babu and K. P. Sridhar
Approximate Computing (AxC) technique is applicable in Error Tolerant Applications (ETA) such as machine learning, deep learning and multimedia processing that demands improved performance metrics. This research work proposes Approximate Full Adder (AFA) with the aim of achieving Ultra Low Power (ULP) consumption, identified as ULP-AFA and a 16-bit Approximate Adder (AA) identified as AA-16. The simulation results of ULP-AFA show 54.2 % and 65.2% reduction of power and PDP over the existing best full adders respectively. AA-16 results shows 36.2% and 24.7% reduction of power and transistor count over the existing best 16-bit AA respectively. The ULP-AFA and AA-16 provided competitive delay and PDP. The proposed ULP-AFA has reliable circuit operation and robustness against noise sources. Moreover, AA-16 is deployed in Deep Learning Accelerators (DLA) and it is found to be efficient. The proposed designs are developed, tested in cadence virtuoso environment at gpdk45nm technology.
Keywords: Approximate Computing, Error Tolerant Applications, Ultra Low Power, GDI, adder, Deep Learning Accelerator