37th International Symposium on Multiple-Valued Logic
Oslo, Norway
May 13—16, 2007
Guest Editor
Bernd Steinbach
Institute of Computer Science
University of Mining and Technology
Freiberg, Germany
p. i-iv
Foreword
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p. 279-294
Characterization of Ternary Cofactors in the Spectral Domain
Claudio Moraga,Milena Stankovic and Suzana Stojkovic
Abstract
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p. 295-320
On Generalized Entropy and Entropic Metrics
Dan Simovici
Abstract
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p. 321-334
The Rough Powerset Monad
P. Eklund and M. A. Galán
Abstract
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p. 335-352
Effective Non-deterministic Semantics for First-order LFIs
Anna Zamansky and Arnon Avron
Abstract
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p. 353-366
Some Polynomials Generating Minimal Clones
Hajime Machida and Michael Pinsker
Abstract
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p. 367-378
Restriction-closed Hyperclones
Boris A. Romov
Abstract
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p. 379-396
Family of Fastest Linearly Independent Transforms over GF(3): Generation, Relations, and Hardware Implementation
B. J. Falkowski, C. C. Lozano and T. Luba
Abstract
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p. 397-414
Automated Reasoning in Some Local Extensions of Ordered Structures
Viorica Sofronie-Stokkermans and Carsten Ihlemann
Abstract
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p. 415-446
Some Criteria for Partial Sheffer Functions in k-valued Logic
Lucien Haddad and Dietlinde Lau
Abstract
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p. 447-466
Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices
Krzysztof S. Berezowski and Sarma B. K. Vrudhula
Abstract
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p. 467-486
Interpretations of the Sampling Theorem in Multiple-Valued Logic
Radomir S. Stankovic and Jaakko T. Astola
Abstract
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p. 487-502
Design of Multiple-valued Arithmetic Circuits Using Counter Tree Diagrams
Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki and Tatsuo Higuchi
Abstract
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p. 503-520
Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions
Yukihiro Iguchi, Tsutomu Sasao and Munehiro Matsuura
Abstract
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p. 521-536
Implementation Complexity of Algorithms for Optimization of Galois Field Expressions for Multiple-Valued Functions
Dragan Jankovic, Radomir S. Stankovic and Claudio Moraga
Abstract
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p. 537-552
QMDD Minimization Using Sifting for Variable Reordering
D. Michael Miller, David Y. Feinstein and Mitchell A. Thornton
Abstract
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p. 553-568
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation
Tasuku Ito and Michitaka Kameyama
Abstract
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p. 569-582
Equalization Techniques for Multiple-Valued Data Transmission and Their Application
Yasushi Yuminaka and Kazuyoshi Yamamura
Abstract
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p. 583-604
GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits
Mozammel H. A. Khan and Marek A. Perkowski
Abstract
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p. 605-618
The Genetic Code as a Function of Multiple-Valued Logic Over the Field of Complex Numbers and its Learning using Multilayer Neural Network Based on Multi-Valued Neurons
Igor Aizenberg and Claudio Moraga
Abstract
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p. 619-632
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits
Nobuaki Okada and Michitaka Kameyama
Abstract
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