Comparative Analysis of Various Logic Families Based One Bit Full Adder Circuits for Energy and EDP Efficient Computing Applications
Mohammed Mahaboob Basha
Addition plays an integral role in mathematical computation, serving as the cornerstone for synthesizing various other operations. Recent years have witnessed an increasing interest in GDI logic circuits as an effective strategy for reducing energy consumption. A high-performance adder plays a pivotal role in developing application-specific integrated circuits (ASICs) to perform multiplication and division. GDI represents an innovative method for designing low-power circuits that minimize power usage, propagation delay and physical footprint of digital circuits. Multiple logic gate circuits were implemented using both GDI and CMOS technologies to design efficient a basic one bit adder. Comparisons among various methods, like CMOS, CPL, 10T, Hybrid adder, TFA and GDI are made by analyzing layout area and device count as well as power dissipation and time delay. Post-layout simulation results demonstrate that the proposed one-bit full adder design has achieved remarkable improvements compared to other published designs, boasting over more than 65% savings in delay time, 56% energy savings and over 90% reductions in Energy Delay Product (EDP) at the cost of 46% of average power consumption by employing just 14 transistors.
Keywords: Transistor count, adders, GDI technique, body bias, area, energy, EDP