Minimization of Leakage Current Control in CMOS Adder Circuits Using Parametric Variations
M. Mahaboob Basha, Srinivasulu Gundala and Rambabu Busi
Deep submicron technologies have raised concerns over power leakage in portable devices with burst mode integrated circuits. Modern high-performance designs are showing an increase in leakage power consumption to meet switching power consumption, according to reports that claim as much as 40% is caused by transistor leakage; without effective strategies in place to control leakage, this number will only continue rising with technological progress; hence the necessity of developing strategies aimed at stopping leakage and optimizing modern designs. To limit leakage, this paper presents an alternative technique called High Threshold Leakage Control Transistor (HTLCT). HTLCT achieves greater reductions in leakage power with higher threshold leakage control transistors; however, at the cost of increasing space and delay requirements. Additionally, this study explores the effect of parametric variations on leakage current and propagation delay in circuits using CMOS technology. Results demonstrate that power leakage is affected by temperature, voltage of supply and aspect ratio while propagation delay has an opposite trend. Leakage power dissipation for an LCT full adder circuit increases approximately more than 6% on temperature, and supply voltages respectively; on the contrary, gate delay decreases approximately less than 9% under identical circumstances.
Keywords: Leakage current, deep submicron, High threshold transistors, aspect ratio, LCT