Temperature Performance Analysis of Hybrid Junctionless Double Gate Transistor
Sachindra Bharti, Rohit Dhiman and Gargi Khanna
In this script temperature analysis on a Hybrid double gate Junctionless transistor with gate engineering has been investigated to improve short-channel effects and gate controllability. The comparative analysis of the proposed device is done by varying the temperature in the range from 200 K to 500 K. The Hybrid Junctionless double gate transistor device at low temperature has provided a Subthreshold Swing of 39.59 mV/decade which is close to less than two-thirds of the ideal value of 60 mV/decade, DIBL at room temperature is found to be 4.21 mV/V. The off current is found as 4.879 × 10-19 A/μm and the switching ratio is very high obtained as 1.563 × 1015. Additionally, the impact of variations in temperature on surface potential, electric field, and electron velocity is also studied. It is found that the electron velocity becomes double as we move from 500 K to 200 K and a very high peak overshoot in electric field is observed at the channel drain interface. Also, the proposed device at room temperature provides nearly 28 % improvement in Subthreshold Swing and 93.42 % improvement in DIBL, and the minimum surface potential is very low then the generic Junctionless double gate transistor.
Keywords: Junctionless transistor – JnLT, double gate junctionless transistor -DG-JnLT, hybrid double gate junctionless transistor- HDG-JnLT, subthreshold swing -SS, electron velocity – Ve, and drain induced barrier lowering -DIBL