p. 283-290
Analysis of FinFET Based 8T SRAM Cell Using Adaptive Voltage Level Techniques
Joshika Sharma, Saurabh Khandelwal and Shyam Akashe
Abstract
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p. 291-303
Optimization of Leakage Current and Leakage Power on 4×4 Array with SVL Technique Employed 7T SRAM Cell in Nanometer Regime
Shalini Singh and Shyam Akashe
Abstract
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p. 305-311
High Performance FinFET Based 3T DRAM with Precise Power Consumption
Shivam Kathairiya and Shyam Akashe
Abstract
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p. 313-321
Slew-Rate Enhancement for a Low-Power Two Stage CMOS OP-AMP in Nanometer Regime
Pragati Gupta, Saurabh Khandelwal and Shyam Akashe
Abstract
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p. 323-334
Analysis of Flash Analog to Digital Converter Using Power Gating Technique
Shivam Dixit and Shyam Akashe
Abstract
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p. 335-347
Design and Performance Analysis of Current Starved VCO for PLL Using SVL Technique
Ankit Srivastava, Maitri Singh, Shyam Akashe and S.R. Nigam
Abstract
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p. 349-357
Optimization of Leakage Parameters of FinFET Based 6T SRAM Cell Using LECTOR Technique
Vishwas Mishra and Shyam Akashe
Abstract
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p. 359-365
Techniques to Minimize Thermal Effects in Typical VLSI Circuits
V. Lakshminarayanan and N. Sriraam
Abstract
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p. 367
Erratum
Abstract
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