Low Power Array (4×4) with Low Leakage, High Performance MTCMOS Based 7TSRAM Cell
Shalini Singh and Shyam Akashe
In this era, 2D scaling of various electronic appliances that are both the logic circuits as well as the memory based devices is eventually reaching their fundamental limits because of aggressive scaling. But as we move on from one technology generation to the other leakage is increasing to an unavoidable extent not only during the standby mode but also during the run time. Earlier leakage power was minimized only for the circuit in standby mode because in active condition the percentage of leakage power was insignificant compared to dynamic power and run time considered about the reduction of dynamic power only but now that is not the case. It has become essential to reduce leakage parameters during the operation of a circuit. Minimum feature sizes, low power consumption, minimum cost and high performance have become the key characteristics of any electronic component. This paper focuses on designing SRAM based array consisting of MTCMOS applied 7T SRAM as its basic unit cell and a comparison has been done with the array comprising of simple 7T SRAM based array without any techniques. The array formed is 4×4 array with a storing capacity of 16 bits. The various leakage parameters have been calculated at different operating mode of read and write and supply voltages of 0.3V, 0.5V, 0.7V and 1V.
Keywords: MTCMOS, high performance, low power, Vt scaling, SRAM array