CA-Based Area Optimized Three Bytes Error Detecting Codes
Jagannath Samanta, Jaydeb Bhaumik and Soma Barman
Cellular automata is already employed by several researchers for designing bit and byte error detecting and correcting codes. Cellular automata based VLSI design is attractive because of its modular, regular and cascadable construction. Reed-Solomon codes are popularly used to detect and correct burst and as well as random errors in different communication systems and storage mediums. In this paper, a simple and modular architecture of cellular automata based (23, 17) encoder and syndrome generator are proposed by employing the regular structure of cellular automata. Proposed design has been optimized using an optimization algorithm. In this work, a new decoding logic circuit has been introduced. Proposed encoder and syndrome generator circuits have less area complexity compared to existing cellular automata based designs. All functional blocks are simulated and synthesized using FPGA based Xilinx 14.3 ISE simulator for Vertex4 target device.
Keywords: Byte error correcting code, reed Solomon code, cellular automata, VLSI, FPGA